1. Field of the Invention
The present invention relates generally to a semiconductor device and, more particularly, to a packaged semiconductor die that becomes a component of a finished multi-chip package, and a manufacturing method thereof.
2. Description of the Related Art
In the electronics industry are continuous demands for improvements of semiconductor products, such as, for example component weight reduction, component miniaturization, increased speed, multi-function abilities, increased performance, higher reliability, and lower costs. Assembly technology of a semiconductor package is one of many important technologies that enable satisfaction of a composite demand including miniaturization, multi-function, and high performance. A multi-chip package (MCP) is one of the recently developed package types to meet the composite demand. The multi-chip package stacks two or more semiconductor chips vertically on a substrate, thereby greatly reducing the area that the semiconductor chips occupy in a finished product set. Consequently, the multi-chip package contributes to an increase in the number of semiconductor chips per unit area.
SIP (System-In-a-Package) technology attempts to assemble, in a package, all semiconductor chips needed for a given unit system. SOC (System-On-a-Chip) technology attempts to integrate within a semiconductor chip all functions needed for a given unit system. SIP technology may be viewed as an intermediate technology between MCP and SOC technologies. Additionally, SIP technology is a key technology for communications modules implementing RF wireless communications, Bluetooth standard (a local area network protocol), high performance personal computer (PC) cards, and cellular phones.
In the case that a bare chip cut from a semiconductor wafer is utilized for a multi-chip package (MCP) including a SIP, a good finished multi-chip package (MCP) requires a precondition that the bare chip is a known good die (KGD—an unpackaged die that has passed a designated series of electrical and burn-in tests and is not shown to be defective so as to be mounted on a multi-chip package). It is difficult to test a bare chip, which does not have a protective means to resist external electrical and mechanical shocks. Because a designated series of tests are performed on a bare chip, a problem exists in that obtaining a known good die is difficult. Consequently, the use of a semiconductor die, which packages a bare chip and protects the bare chip from external electrical and mechanical shocks, has been suggested in testing the bare chip. A good packaged die having successfully passed a designated series of tests may be utilized as a component of a semiconductor package.
FIG. 1 is a sectional view showing a conventional packaged semiconductor die. As shown in FIG. 1, a packaged semiconductor die 100 comprises a die substrate 120, a semiconductor chip 110, wire 160, and a sealant 170.
The die substrate 120 comprises an insulating substrate 121 of a platy form and having an upper surface and a lower surface, a substrate pad 122 formed on the lower surface of the insulating substrate 121, and a signal pad 123 and test pad 124 both formed on the upper surface of the insulating substrate 121. The signal pad 123 may be connected to a wire or bump for external connection. The test pad 124 may act as an external interface terminal for testing the packaged semiconductor die 100.
The semiconductor chip 110 is attached to the lower surface of the die substrate 120, and comprises a chip substrate 111, a chip pad 112 formed on the chip substrate 111, and a passivation layer 113 stacked on the chip substrate 111 so as to expose the chip pad 112.
The substrate pad 122 and chip pad 112 are electrically connected with wire 160, which is commonly made of gold (Au).
The sealant 170 seals the semiconductor chip 110 and wire 160 as shown in FIG. 1, and protects them from external electrical and mechanical shocks. In one embodiment, the sealant 170 is made of epoxy resin.
However, a finished semiconductor package that has been verified to be a known, good, package may not be utilized for the conventional packaged semiconductor die. For example, a semiconductor chip, such as a bare chip as shown in FIG. 1, has to be packaged separately and this separate packaging may cause a problem, such as, increasing the required time and cost in manufacturing semiconductors. Additionally, in the case that a semiconductor chip is tested in a packaged semiconductor die of a land grid array (LGA) type as shown in FIG. 1, the test pad 124 may be easily broken by a test contact pin (not shown) thereby disrupting the test process. Furthermore, a test failure after packaging a semiconductor die may cause not only the waste of effort invested in packaging, but also the reduction of efficiency in manufacturing semiconductors.
Accordingly, the object of the present invention is to provide an improved packaged semiconductor die and its manufacturing method which may be utilized for various existing semiconductor package types.